This invention relates, in general, to translator circuits, and more particularly to translator circuits which interface digital circuits operating at different voltage levels.
Integrated circuit technology, in general, is shifting towards lower operating voltages. Wafer processing advances allow for the fabrication of smaller devices which increase transistor densities within a given area. The smaller devices cannot withstand the standard operating voltage used in the industry. For example, CMOS digital circuitry currently operates at 5 volts. In the future this supply voltage standard could drop to a voltage somewhere between 2.7 and 3.3 volts. Other factors besides wafer processing issues such as reduced power dissipation, new semiconductor processes/materials, or battery operated applications may further fuel a push to lower operating voltages.
It is critical that circuits operating at the two different voltage supply standards (3 or 5 volts) can still interface with one another. The new lower voltage standard would be extremely difficult to integrate into mainstream integrated circuit sales if they were not compatible with the current voltage standard. A translation circuit which interfaces circuitry operating at two different voltage levels must meet several requirements to minimize impact it has on a circuit design. Some of these requirements of the translation circuit are 1) speed (must add minimal delay to system), 2) area (must not take up a significant portion of the design), 3) simplicity (the translator must not be a yield problem), and 4) power dissipation. Most translator circuits currently used fail in one or more of these areas. Thus, it would be of great benefit if a translator circuit could be designed which is fast, uses minimal silicon areas, is simple, and does not dissipate an appreciable static current.